One conventional non-volatile memory includes a plurality of gate electrode structures each of which includes a floating gate electrode and a control gate electrode. In the non-volatile memory, a plurality of cell arrays is provided in which source diffusion layers are commonly collected at various points corresponding to a few bits of data and source contacts are commonly connected at various points corresponding to a few bits thereof to connect source lines with each other. In such a conventional non-volatile memory, however, exclusive regions for source lines at every point corresponding to a few bits thereof are required, so that the degree the non-volatile memory can be scaled-down is limited.
Recently, an advanced non-volatile memory has been developed in which a plurality of source contacts are provided at each point corresponding to each bit of data, and the source contacts and bit contacts are formed through a self-alignment technique via source and drain diffusion layers. This type of a non-volatile memory has been described at Y. HISAMUNE et al., IEDM Technical Digest, 1989, pages 583-586.
The conventional non-volatile memory includes a plurality of cell array regions arranged in parallel with each other and a plurality of control gate electrodes arranged orthogonally to the cell array regions. Each of the cell array regions includes a plurality of floating gate electrodes, each of which is positioned at each of the crossing points with respect to the control gate electrodes; a plurality of pairs of source and drain diffusion layers, each of the pairs positioned to sandwich each of the control gate electrodes; source contacts, each of which is formed on each of the source diffusion layers; and drain contacts, each of which is formed on each of the drain diffusion layers, both of the contacts are formed through a self-alignment technique via the control gate electrodes.
The conventional non-volatile memory also includes a plurality of source lines arranged in parallel with the control gate electrodes in which each of the source lines is connected with each of the source diffusion layers through each of the source contacts, a plurality of drain pads formed separately above each of the drain diffusion layers to be connected therewith through each of the drain contacts, a plurality of bit contacts formed within each of the drain pads, and a plurality of bit lines arranged in parallel with the cell array regions in which each of the bit contacts is connected with each of the drain diffusion layers through each of the bit contacts and the drain pads, respectively.
According to the conventional non-volatile memory, however, there is a disadvantage in that a scale-down of the cell size thereof is difficult, because the size of the drain pad is required to be considerably large as the bit contact is formed thereon. In more detail, the size l, which is a length of one side of a square of the drain pad is required to fulfill the following relation: EQU l&gt;.lambda.+.DELTA..lambda.+.DELTA.l+.delta.
where .lambda. is the size of the bit contact (a length one side of a square), .DELTA..lambda. is a patterning gap between the real size of the bit contact and the pattern size of a mask (extension from the mask pattern), .DELTA.l is a patterning gap between the real size of the drain pad and the pattern size of the mask (narrowness from the mask pattern), and .delta. is the alignment shift of the bit contact to the drain pad. If the gap between the adjacent drain pads is defined as S.sub.1, the minimum cell size in the direction parallel to the control gate electrode becomes l+S.sub.1. If the size of .lambda. and S.sub.1 is determined to be the minimum design size .eta., the minimum cell size in the direction parallel to the control gate electrode becomes 2.eta.+.DELTA..lambda.+.DELTA.l+.delta.. Therefore, the degree of scale-down of the cell size is limited by the factors .DELTA..lambda., .DELTA.l and .delta. which are dependent on the process for fabricating the non-volatile memory.
Furthermore, the source line and the drain pad are required to be formed to over-lap with the control gate electrode in the direction parallel to the bit line, because the source and drain contracts are formed through self-alignment via the control gate electrode. In such a case, since the source line and the drain pad are made of the same conductive thin layer, the gate length L of the control gate electrode is required to fulfill the following relation: EQU L&gt;S.sub.2 +2.gamma.
where .gamma. is the length of over-lapped regions between the control gate electrode and the source line and between the control gate electrode and the drain pad, and S.sub.2 is a gap between the source line and the drain pad. If S.sub.2 is determined to be the minimum design size .eta., the minimum gate length L of the control gate electrode becomes .eta.+2.gamma., so that it is difficult to achieve a gate length L to be the minimum design size .eta..